In this test 5 buffers were acquired, as shown in the top tool bar.
DEBUGGIN XSCOPE SERIAL
The Accumulate button in the serial decode panel is switched on and is therefore highlighted in blue. Each time a valid trigger condition occurs a record will be stored in a new buffer.įigure 6 illustrates a more complex data transfer sequence. We will also see how PicoScope can split the acquisition memory into a number of buffers from 1 to 10,000. This can be done using the Accumulate option in the serial decode window. In more complex systems we may want to acquire multiple blocks of I☬ data transfers. Acquisition of multiple I☬ block transfers 1 (Appendix B - References) for details of the data format expected by the AD5325 DAC.įigure 7: Sequence of I☬ data transfers 7. The final two columns indicate the timings of each transfer.Column six shows that each transfer of address and data was acknowledged.Bytes 9 and 10 show CH B was selected with data 02, and a different output level was requested by the next two bytes (2C23).In this case the first data byte 01 addresses CH A of the DAC, and 2C and 11 are the data (2C11) to be sent to the DAC to request a new output level of 1880 mV. The fifth column displays the decoded data.The next column defines if the data is a read or write.The third column is the decoded address, in this case 0C which is the address of the DAC.The second column shows the type of packet or event: address, data, start or stop.
DEBUGGIN XSCOPE PLUS
The first column is the packet number assigned by PicoScope: in this case there are 12 packets of address and data bytes plus start/stop conditions.For a clearer view of this data (Figure 5). This panel is the decoded I☬ serial protocol display. It is much faster to use the I☬ decoding provided by PicoScope as displayed in the lower panel. It would be possible to manually decode the I☬ commands from this display if the protocol of the bus were applied to each data byte, but this would be laborious and errors could easily occur. This display would show if any error in data had occurred, which could have been due to noise or interference from other signals. This panel displays the raw digital data on the SDA serial data and SCL serial clock lines of the I☬ bus. Two data bytes for the channel DAC value.Just below the analog waveforms, an overview of the two I☬ data transfers is displayed. Again, the actual point when the level switches is when the DAC has received the three data bytes. The vertical scale factor for this waveform is shown in red on the right–hand side of the display.
The lower, red trace shows the CH B output voltage level switching from 1.9 V to 0.6 V. This is followed by the acknowledgement bit and another transfer. The point in time where the voltage step occurs is the end of the third byte of I☬ data. These voltage values can be read more accurately with the cursors that are available on the instrument (Figure 3). The upper, blue trace shows the CH A output voltage switching from 1.9 V to 0.6 V. The middle panel displays two digital channels D0 and D1, and the lower panel displays the I☬ decoded data. The display is split into three panels: the upper panel displays the two analog channels A and B plus an overview of the I☬ bus transfer data.
The data was acquired from an I☬ bus data transfer. Figure 3: Display with XY cursors measuring switching amplitude and time 1.1 Analog displayįigure 2 shows the screen display of the PicoScope MSO.
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